1. Field of the Invention
The present invention relates to semiconductor mono lithically integrated circuits and, more particularly, to complementary type integrated circuits comprising MISFET or, more commonly, P-channel and N-channel MOSFET structures, that is CMOS structures.
2. Description of the prior art
The commercial utilization of CMOS integrated circuits has gradually consolidated, interesting almost every kind of application of microelectronics. Today such a tech nology is commercially utilized in at least three quarters of nonbipolar integrated devices produced. One of the most sensitive aspects of CMOS technology has always been the unavoidable presence of parasitic bipolar structures which, under particular conditions, may become SCR connected, originating a regenerative phenomenon known as "latch-up" which often has a destructive consequence. The latch-up has been for years one of the main factors in delaying the commercial application of CMOS technology, being the competing technologies, namely the bipolar and single channel MOS technology, exempt from this phenomenon. Many preventive, reductive and/or protective techniques against latch-up have been developed and today the latch-up has been practicaly eliminated in CMOS integrated circuits with a single supply, which account for almost the totality of digital integrated circuits produced. On the other hand CMOS devices are widely utilized nowadays for integrated circuits performing mixed functions (analogic-digital) wherein they have practically replaced single channel MOS devices.
In this area of application, the supplies are almost always two: a positive one (VCC=+5V) and a negative one (VBB=-5V) in respect of ground (GND=0V). Moreover in this area of application, a good decoupling between digital and analogic parts of the integrated circuit as well as between different circuit sections which function within the integrated devices (e.g. transmission and reception circuit sections) is mandatory. It follows that for A/D and D/A converters and in general for analogic/digital integrated circuits, the supplies are kept "clean" by means of capacitors connectors between one supply and the other and between each supply and ground. These capacitors have necessarily relatively high values of capacitance (up to 100 micro Farads) and therefore once charged they may cause strong current peaks, i.e. they are able to supply high currents even if for extremely limited periods of time.
Such a typical circuit arrangement is shown in FIG. 1.
It is easily understood that with an increasing number of supplies, the problem of preventing latch-up becomes more severe. The probability that, as a consequence of a particular sequence of application of the supply voltages, one of the integrated circuit pins be polarized in a relatively incorrect way, thus provoking a direct biasing of the internal junctions of the integrated device (condition which may cause latch-up), increases.
For example, if the integrated device is a P-Well CMOS, when the -5V supply voltage is applied with a certain delay in respect of the +5V supply voltage, the temporary "floating" condition of the negative supply pin of the integrated circuit reflects itself as a positive biasing of the VBB terminal (pin) by virture of a capacitance subdivision of the VCC voltage (equal to +5V), in accordance with the relation: ##EQU1##
Therefore, if C2=CO; then VBB=+2,5V for the whole period of time during which to the relative pin of the integrated circuit corresponding to the VBB supply is not imposed the correct supply voltages of -5V.
Also the expedient of using a capacitor CO much greater than the capacitor C2 is not always practicable. It is also easily understood that, for an integrated circuit manufacturer it is difficult to foresee the uses which will be made of the integrated circuit itself and therefore which capacitors will be used, unless imposing stringent application specifications which are hardly acceptable by the users.
From the point of view of an integrated circuit manufacturer, a typical situation is that shown in FIG. 2, wherein the capacitance between a P-Well region and the substrate is much greater than the capacitance between an N+ diffused region and the P-Well (C.sub.p-Well/sub &gt;&gt;.sup.C.sub.N+/P-Well).
In such a situation, the P-Well potential will rise up to a value very close to the VCC voltage and the P-Well/N+junction will result direct biased if within the P-Well tub there are grounded N+ diffusions. Such grounded diffusions almost certainly exist because for the designer of integrated circuits not having available N-channel MOS transistors with a source connected to ground formed in a substrate which under steady conditions must be at a VBB potential (-5V) would be a hardly tolerable restraint.
Therefore the designer of integrated circuits must protect these areas, but the protection against latch-up has a definite cost in terms of area so that this reflect itself in a certain limitation of the number of N-channel transistors with grounded source which may be economically used in designing the integrated circuit.
Shown in FIG. 3, is what may happen in a integrated circuit with two supplies when on an assembly card other components are connected to the two supplies and a retarded application of the VBB voltage in respect to the VCC voltage has provoked the direct biasing of internal junctions (diodes) P-Well/N+.
An eventual presence of an operational amplifier, as schematically shown in FIG. 3, provides a current path: VCC - operational amplifier - VBB - P-Well/N+ diode - GND; which is responsible for triggering the latch-up condition with a consequent possible destruction of the integrated circuit. In a case of this kind in fact, the current injected is relatively large even in absence of capacitors connected across the supplies.
Naturally, the above noted problems are present also in a N-Well CMOS device when the positive supply (VCC) is provided with a certain delay in respect to the negative supply voltage (VBB). In this case N-Well tubs and P+ diffusions substitute P-Well tubs and N+ diffusions, respectively, in the relative figures and in the above discussion.
A common advice still given by integrated circuit manufacturers through data sheets, is that of using a Schottky diode connected as shown in FIG. 3 by means of the phantom (dash line) figure (i.e. between VCC and GND in the case of a N-Well CMOS), or of providing a capacitor CO much greater than C2 and C1 in case disturbances by-pass capacitors are used on the supplies.
Users, on their part, build cards intended for two supplies P-Well CMOS integrated circuits, purposely having the terminals of the tracks relative to the VBB voltage projecting more than the ground terminals and, particularly, than those relative to the VCC voltage so that, upon inserting the card carrying P-Well CMOS integrated devices, the supply voltages be applied according to the following sequence: VBB=-5V, GND=0V and VCC=+5V. Upon extracting the card, the same supply voltages will be disconnected according to an inverted sequence. Obviously such a solution avoids latch-up problems only during insertions and extractions of the card. Moreover, such an expedient will cease to be useful when, soon, P-Well type as well as N-Well type CMOS integrated circuits will be utilized together on a same system card.